1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits and semiconductor devices, and, more particularly, to the formation of integrated inductors in the context of CMOS manufacturing techniques.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of N-channel transistors and P-channel transistors are formed on a substrate including a crystalline semiconductor layer.
In some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-20 nm or less, gate structures that include a so-called high-k dielectric gate insulation layer and one or more metal layers that function as the gate electrode have been implemented that provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/polysilicon gate structure configurations.
In principle, there are two well-known processing methods for forming a planar or 3D transistor with a high-k/metal gate (HK/MG) structure: (1) the so-called “gate-last” or “replacement gate” technique; and (2) the so-called “gate-first” technique. In the replacement gate technique, a so-called “dummy” or sacrificial gate structure is initially formed and remains in place as many process operations are performed to form the device, e.g., the formation of doped source/drain regions, performing an anneal process to repair damage to the substrate caused by the ion implantation processes and to activate the implanted dopant materials. At some point in the process flow, the sacrificial gate structure is removed to define a gate cavity where the final HK/MG gate structure for the device is formed. In general, using the “gate-first” technique involves forming a stack of layers of material across the substrate, wherein the stack of materials includes a high-k gate insulation layer, one or more metal layers, a layer of polysilicon and a protective cap layer, for example, silicon nitride. Thereafter, one or more etching processes are performed to pattern the stack of materials to thereby define the basic gate structures for the transistor devices.
It is important to note that, in general, the formation of transistor devices is part of an overall integrated processing of a variety of devices, such as transistors, fuses, resistors, etc. Analog electronic circuits, especially those operating at radio frequency, may include inductors and transformers for filtering, frequency mixing, oscillators, interstage radio frequency coupling and high frequency pulse coupling. Transformers are adapted to pass mating current (AC) signals and block direct current (DC). Inductors and transformers have been fabricated in many forms, from large iron core transformers used at power frequencies to air core inductors used at radio frequencies. Radio frequency inductors and transformers have been enclosed in metal cans, non-conductive coil forms, open construction, fabricated onto a printed circuit board and the like.
More recently, with the advent of integrated circuits and electronic miniaturization, the need arose to reduce the size of external discrete components necessary with an integrated circuit product, preferably elimination of any discrete components was a primary goal. More and more, formerly discrete components were fabricated onto integrated circuits, i.e., resistors, capacitors and inductors, for both size and cost reasons. Inductors were especially a problem because of the physical size and geometry normally required for an effective inductor over a desired range of frequencies. In general, inductors are important components in many of the building blocks in wireless communication systems, such as RF bandpass fillers, oscillators, impedance matching networks and/or emitter degeneration circuits. Wireless communication standards place stringent requirements on performance and operating parameters, such as noise interference/immunity and power consumption. To accommodate the stringent requirements, high Q inductors are needed.
An inductor fabricated on an integrated circuit substrate generally has been formed in the shape of a spiral coil structure in a single metal layer on an insulation layer using typical integrated circuit fabrication techniques. This spiral coil structure requires a substantial area of the silicon integrated circuit substrate, typically, for example, 200 μm×200 μm. The spiral coil structure also suffers from parasitic capacitive influence from the integrated circuit substrate on which it is fabricated. Fabrication on an integrated circuit substrate of an efficient transformer (two inductors electromagnetically coupled together) is also extremely difficult using spiral coil structure shapes because of the physical size required and the inherent parasitic capacitance which may render the resulting transformer structure inefficient or ineffective for a desired purpose.
Thus, there is, particularly, a need for the formation of a high Q inductor with reduced spatial dimensions as compared to conventionally BEOL manufactured inductors comprising planar circular metal strips. More particularly, there is a need to integrate the formation of space-saving inductors in the overall CMOS manufacturing process.
In view of the situation described above, the present disclosure provides techniques that allow for the formation of space-saving inductors within the CMOS manufacturing process, in particular in the context of the gate-first manufacturing flow of HK/MG transistor devices.